Recently, there has been an increasing demand for liquid crystal display devices for use in large-screen liquid crystal TV sets as well as for use in portable telephones (such as mobile phones or cellular phones), notebook PCs, and monitors. As these liquid crystal display devices, an active matrix driving liquid crystal display device capable of performing high-definition display is employed. First, referring to FIG. 10, a typical configuration of the active matrix driving system liquid crystal display device will be outlined. FIG. 10 schematically shows a main configuration connected to a pixel in a liquid crystal display unit, using an equivalent circuit.
Generally, a display unit 21 of the active matrix driving liquid crystal display device includes a semiconductor substrate, an opposing substrate, and a liquid crystal sealed in between these two substrates by opposing these two substrates. On the semiconductor substrate, transparent pixel electrodes 214 and thin-film transistors (TFTs) 213 are arranged in a matrix form (of 1280×3 pixel rows×1024 pixel columns in the case of a color SXGA panel, for example). One transparent electrode 217 is formed on an entire surface of the opposing substrate.
On the semiconductor substrate, data lines 212 and scan lines 211 are wired in the form of a grid.
To a data line 212, a plurality of level voltages (gray scale signal voltages) applied to each pixel electrode 214 are supplied from a data driver 23.
To a scan line 211, a scan signal is supplied from a gate driver 22.
A TFT 213 having a switching function is ON/OFF controlled by the scan signal. When the TFT 213 is turned on, a gray scale signal voltage corresponding to a display data signal on the data line 212 is applied to a corresponding pixel electrode 214. Transmittance of the liquid crystal is changed by a potential difference between each pixel electrode 214 and the opposing substrate electrode 217, and even after the TFT 213 has been turned off, the potential difference is held by a liquid crystal capacitor 215 and an auxiliary capacitor 216 for a certain period, thereby displaying an image.
Rewriting of data of one screen is performed in one frame period (of approximately 0.017 seconds, usually). Data is successively selected every pixel row (every line) by each scan line, and a gray scale voltage signal is supplied to the pixel electrode 214 through each data line within a selection period.
A display controller 24 converts an information signal received from a microprocessor (a CPU) not shown to a timing control signal, display data, or the like.
The gate driver 22 and the data driver 23 are controlled by the display controller 24. A clock signal CLK and a control signal are supplied from the display controller 24 to each of the gate driver 22 and the data driver 23, and the display data is supplied to the data driver 23. Currently, digital data has been mainly employed as video data.
In large-sized liquid crystal devices, the display controller 24, gate driver 22, and data driver 23 are composed of specific LSIs, respectively. Each of the gate driver 22 and the data driver 23 is composed of a plurality of LSIs in accordance with a resolution of the display unit 21. In case the display unit 21 has a high resolution, the display controller 24 is also composed of a plurality of LSIs. Signal transmission between the display controller 24 and one of the gate driver 22 and data driver 23 is usually performed through a printed circuit board.
In the signal transmission (an interface) between the display controller 24 and the data driver 23, a large amount of data must be transmitted.
For this reason, recently, a high-speed interface using a small-amplitude differential signaling has been adopted for transmission of the large amount of display data.
In the small-amplitude differential signaling system, data is serially transmitted, thereby greatly reducing the number of signal lines on a printed circuit board. In order to suppress EMI (Electro Magnetic Interference) noise caused by a high transmission rate, a small-amplitude signal is used. This makes the system to be a configuration where not only the EMI noise is suppressed, but also immunity to an influence of external noise is provided. Further, by using serial transmission, the small-amplitude differential signaling system can reduce the number of signal lines on the printed circuit board and a cost of the printed circuit board.
As the small-amplitude differential signaling,                LVDS (Low Voltage Differential Signaling), RSDS (Reduced Swing Differential Signaling: a trademark of National Semiconductor Corporation) which is a differential voltage signaling system,        CMADS (Current Mode Advanced Differential Signaling) which is a differential current signaling system, and the like have been proposed and put into practical use.        
In the small-amplitude differential signaling system, a data receiver circuit (receiver circuit) 29 of a data driver 23 receives a small-amplitude differential signal. More specifically, the data receiver circuit 29 converts a small-amplitude differential voltage signal with the amplitude thereof being approximately 50 mV to 400 mV to an amplitude (of 1.5V to 3.3V) in accordance with a power supply voltage of a logic circuit (not shows) within the data driver 23. When the low-voltage differential signal is a differential current signal, the differential current signal is subject to current-to-voltage conversion in an input stage of the data receiver circuit.
FIG. 12 is a diagram showing an example of a configuration of a typical data receiver circuit (receiver circuit). This data receiver circuit amplifies and converts a small-amplitude differential input signal to a single ended digital signal with a power supply voltage amplitude (between VDD and VSS). Referring to FIG. 12, this data receiver circuit includes a differential pair composed of PMOS transistors M81 and M82 and a current source M80. Sources of the PMOS transistors M81 and M82 are connected in common to the current source M80, and gates of the PMOS transistors M81 and M82 are connected to an input pair (1, 2) supplied with a small amplitude differential signal (IN1, IN2). The current source M80 is connected between a high-voltage power supply VDD and the sources of the differential pair (M81, M82) connected in common. The current source M80 supplies a current to the differential pair (M81, M82). A differential pair composed of transistors Ma and Mb is expressed by a “differential pair (Ma, Mb)”.
Between an output pair (drains of the PMOS transistors M81 and M82) of the differential pair (M81, M82) and a low-voltage power supply VSS, diode-connected NMOS transistors M83 and M84 are connected, respectively.
The data receiver circuit includes an NMOS transistor M88 with a gate thereof connected to a gate (a node 3) of the diode-connected NMOS transistor M83, a source thereof connected to the low-voltage power supply VSS, and a drain thereof connected to an output terminal 6. The NMOS transistors M83 and M88 constitute a current mirror.
The data receiver circuit includes an NMOS transistor M85 with a gate thereof connected to a gate (a node 4) of the diode-connected transistor M84 and with a source thereof connected to the low-voltage power supply VSS. The NMOS transistors M84 and M85 constitute a current mirror. A current mirror composed of transistors Mc and Md is expressed by a “current mirror (Mc, Md)”.
The data receiver circuit includes a PMOS transistor M86 with a source thereof connected to the high-voltage power supply VDD and a drain and a gate thereof connected to a drain of the NMOS transistor M85, a PMOS transistor M87 with a gate thereof connected to the gate of the diode-connected transistor M86, a source thereof connected to the high-voltage power supply VDD, and a drain thereof connected to the output terminal 6. The PMOS transistors M86 and M87 constitute a current mirror.
Next, an outline of an operation of the data receiver circuit in FIG. 12 will be described.
The differential pair (M81, M82) receives a differential input voltage (IN1, IN2) and outputs currents Ia and Ib to an output pair thereof. The current Ia is supplied to the NMOS transistor M83 of the current mirror (M83, M88), and a current Ic is output from the NMOS transistor M88.
The current Ib is supplied to the NMOS transistor M84 of the current mirror (M84, M85). A current is temporarily supplied from the NMOS transistor M85. The current is further supplied to the PMOS transistor M86 of the current mirror (M86, M87). Then, a current Id is output from the PMOS transistor M87.
A potential at an output terminal 6 varies according to a difference between the currents Ic and Id, and is converted to a digital signal having a power supply voltage amplitude determined by a high-voltage power supply VDD and a low-voltage power supply VSS. A ratio of an input current to an output current of each current mirror may be set to be one or more. A current ratio of the current Ia to the current Ic is set to be substantially comparable to that of a current ratio of the current Ib to the current Id.
When the signal IN1 of the differential input signal (IN1, IN2) is low (L) and the signal IN2 is high (H), a gate-to-source voltage of the PMOS transistor M81 becomes greater than a gate-to-source voltage of the PMOS transistor M82. The current Ia of the differential pair (M81, M82) becomes greater than the current Ib.
Thus, the current Ic corresponding to the current Ia of the output pair of the differential pair (M81, M82) becomes greater than the current Id corresponding to the current Ib of the output pair of the differential pair (M81, M82). Then, the current Id that discharges the output terminal 6 becomes greater than the current Ic that charges the output terminal 6. A voltage of an output signal OUT of the output terminal 6 changes to the voltage of the low-voltage power supply VSS.
When the signal IN1 is high (H) and the signal IN2 is low (L), a magnitude relationship among respective current signals is inverted (in which Ia<Ib, Ic<Id). Then, the voltage of the output signal OUT changes to the voltage of the high-voltage power supply VDD.
The output signal (a serial binary signal) of the output terminal 6 is converted to a parallel signal by a serial-to-parallel converter circuit (not shown) in a subsequent stage, in response to a timing control signal and finally is converted to a data signal of a drive frequency that supports driving of a data line.
Patent Document 1 discloses a configuration in which a current that flows through a load circuit of an n-channel differential pair is folded by a current mirror and flown into an n-channel transistor that forms a load circuit of a p-channel differential pair in a rail-to-rail differential amplification circuit.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-11-150427